SOC Verification Using System Verilog
A comprehensive course that teaches System on Chip design verification concepts and coding in System Verilog Language
This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in System Verilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.
Your Instructor
Experienced Verification Engineer with 16+ years of experience, Intel Alumni, passionate in continuous learning and knowledge sharing (www.verificationexcellence.in)
Co-Author of the book "Cracking Digital VLSI Verification Interview : Interview Success" - A Golden reference guide for VLSI engineers at all experience level
Teaching Online courses on SystemVerilog, Assertions, Coverage, UVM
Always willing to extend a helping hand to those in need. Raise a question or send me a message and would be happy to help and stay connected
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Course Curriculum
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StartVerification - What , Why and How ? (7:23)
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StartVerification - Planning, Approaches, Metrics (9:17)
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StartVerification Methodologies - Simulation , Formal and Assertions (13:57)
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StartDirected Vs Constrained Random Verification and Coverage (12:59)
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StartOther Trends - HW+SW Verification and Emulation (8:14)
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PreviewQuiz 2: Test your Verification Concepts
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StartExercise 1: Case Study with a Design to be verified (9:08)
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StartHistory and Overview of System Verilog (6:20)
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StartLanguage Constructs: DataTypes And Operators (10:41)
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StartLanguage Constructs: Loops and Flow control (6:59)
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StartSystem Verilog Tasks and Functions (5:06)
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PreviewQuiz 3 : Test your SystemVerilog Basics
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StartSV Arrays and Queues (13:53)
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StartExercise 2: Coding of a design to be verified (18:39)