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Learn System Verilog Assertions and Functional Coverage
Welcome and Overview
Introduction and Overview (2:21)
Quiz1 - Test your basics
System Verilog Assertions - Basics and Sequences
Introduction to Assertions (11:00)
SVA Basics - Immediate and Concurrent Assertions (14:56)
SVA Basics - Sequences and Properties (14:48)
Sequence Operators - Repeat operators (10:11)
Sequence Operators - AND , OR (11:49)
Sequence Operators - First_match, throughout and within (10:45)
Sequence Operators - if..else, ended (9:04)
Quiz 2 - Test your knowledge on operators
Sequences - Usage of Local Variables and Subroutines (11:19)
Sequences - Sample Value Functions (13:06)
Quiz 3 - Test your SVA knowledge
Sequences - System Tasks and Functions (7:42)
Exercises for Sequences (7:39)
System Verilog Assertions - Properties and Clocking
SVA Properties - Basics and Types (11:27)
SVA - Recursive Properties (10:56)
Clock Resolution and Multiple clk properties (12:58)
SVA - Binding and usage of expect statement (10:47)
SV Assertions - Tips and Best Practices (8:26)
Exercises for Assertions and Properties (8:55)
Quiz 4 - Test your Assertions knowledge
System Verilog - Functional Coverage Coding
Introduction to Coverage (13:40)
SV Covergroups and Coverpoints - Basics (15:01)
Coverage Bins - Auto, wildcard, illegal and ignore bins (15:01)
SV Cross Coverage (15:01)
SV Coverage options and usage (8:10)
Coverage pre-defined methods and performance implications and Cover property (13:44)
Quiz 5 - Testing Functional Coverage
Exercises for Functional Coverage (5:40)
Summary and Wrapup
Quiz 6 - Test your skills
Course Summary and Thank you (12:08)
Quiz1 - Test your basics