The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.
This course teaches the basic concepts of two (similar) methodologies - OVM and UVM - and helps you get started on coding and building actual testbenches from grounds up.
Plenty of examples along with assignments (all of examples uses UVM) - quizzes and an optional final online examination and certificate will make your learning thorough.
Experienced Verification Engineer with 16+ years of experience, Intel Alumni, passionate in continuous learning and knowledge sharing ()
Co-Author of the book "" - A Golden reference guide for VLSI engineers at all experience level
Teaching Online courses on
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